This invention relates to sources for generating high-frequency electrical signals and, more particularly, to frequency synthesizers for generating swept radio-frequency (RF) signals, including signals at microwave frequencies. Specifically, one embodiment of the invention provides a swept synthesized source having a phase-lock loop for providing improved control of the frequencies generated by the swept synthesized source and preferably also provides reduced phase-lock loop acquisition time and improved stability for a low-frequency synthesizer incorporated into the swept synthesized source to yield a swept synthesized source having improved frequency accuracy and reduced phase noise.
A block diagram of a conventional swept synthesized source is shown in FIG. 1. Such a swept synthesized source generates an electrical signal having a selectively variable frequency. Typically, the frequency is varied, or swept, either continuously or in discrete steps from one frequency, known as the "start frequency," to a higher frequency, known as the "stop frequency," the range of frequencies from the start frequency to the stop frequency being known as the "frequency span."
The typical swept synthesized source, generally indicated by the numeral 10 shown in FIG. 1, comprises a microwave electronically tunable oscillator 12, a frequency sampler 14, a low-frequency synthesizer 16, a phase/frequency detector 18, a reference oscillator 20, a loop filter/signal conditioning circuit 22, an electronic pretuning circuit 24, such as a digital-to-analog converter (DAC), and means to open and close the phase lock loop, such as a switch 26. Operation and synchronization of the low-frequency synthesizer 16, the pretuning circuit 24, and the switch 26 are controlled by a controller 28, such as a microprocessor.
Considered in more detail, in order to lock to any selected start frequency within the operating range of the swept synthesized source 10, the microwave oscillator 12 is pretuned near this frequency with the switch 26 operated by the controller 28 to the dotted line position indicated in FIG. 1, so that the main phase-lock loop of the swept synthesized source is open, and a tuning input of the microwave oscillator is connected to the pretuning circuit 24. Also, the low-frequency synthesizer 16 is set to its lowest frequency by the controller 28.
Once pretuning is complete, the switch 26 is operated to the solid line position indicated in FIG. 1, so that the main phase-lock loop is closed. The selected start frequency is attained when the microwave oscillator 12 locks on to the proper comb tooth that appears in the output of the sampler 14, as is well known. This occurs when the signal produced by the phase/frequency detector 18 reaches a null during operation of the main phase-lock loop after the loop is closed. The low-frequency synthesizer 16 is then swept by the controller 28 up to a frequency which produces the selected stop frequency of the microwave oscillator 12.
In order for the swept synthesized source 10 to be swept from the selected start frequency to the selected stop frequency, the frequency of the low-frequency synthesizer 16 is incremented by the controller 28 as will be described shortly. This causes the signal produced by the phase/frequency detector 18 to deviate from the null condition and feed an error voltage to the tuning input of the microwave oscillator 12, which drives the microwave oscillator to operate at a higher frequency. Once this higher frequency is attained, the main phase-lock loop operates so that the phase/frequency detector 18 again reaches a null condition. This process is repeated with the frequency being increased, either continuously or in discrete steps, until the selected stop frequency is reached.
The swept synthesized source 10 of the type shown in FIG. 1 has several known limitations. Most importantly, it is imperative to pretune accurately so that the microwave oscillator 12 does not lock on to the wrong comb tooth of the sampler 14.
However, there are inherent problems with the conventional pretuning technique described above. Specifically, the required pretune voltage produced by the pretuning circuit 24 is typically derived from a pretune calibration algorithm. For example, in the case where the pretuning circuit 24 is a DAC, the pretune calibration algorithm is based on a transfer function of selected pretune frequency versus required DAC setting. The voltage produced by the DAC in response to this DAC setting is converted to a current that is fed to the tuning input of the microwave oscillator 12 to drive the microwave oscillator.
Unfortunately, the microwave oscillator 12 is typically a yttrium-iron-garnet (YIG) oscillator or other tunable device comprising magnetic material. Therefore, the microwave oscillator 12 has a hysteresis in its tuning characteristic. This means that a given pretuning current produced in response to the DAC voltage can yield a range of output frequencies dependent on the previous amount of tuning current present.
Also, another difficulty results from the non-linear pretuning curve for the tuning current versus actual pretune frequency transfer function for different frequency bands of the microwave oscillator 12. The conventional swept synthesized source 10 employs a piece-wise linear approximation to this curve, requiring derivation of several segment endpoints during the pretune calibration. However, this pretune calibration is affected by changes in time and temperature.
Consequently, the accuracy of the swept synthesized source 10 in generating a selected pretune frequency can be relatively low due to the hysteresis characteristic of the microwave oscillator 12. Additionally, the repeatability with which the swept synthesized source 10 can generate that selected pretune frequency is significantly affected over changes in time and temperature. Therefore, a swept synthesized source is needed to overcome these limitations.
Additionally, the low-frequency synthesizer 16 can comprise a synthesizer having a conventional configuration shown in the block diagram of FIG. 2. As shown in FIG. 2, a phase-lock loop for the low-frequency synthesizer 16 typically comprises another reference oscillator 52, another phase/frequency detector 54, integrator(s) 56, 58, a voltage controlled oscillator (VCO) 60, and a frequency divider 62. The VCO 60 is phase-locked to the reference oscillator 52 by using the phase-lock loop for the low-frequency synthesizer 16. The frequency of the VCO 60 is N times the frequency of the reference oscillator 52, where N is the divide number of the frequency divider 62 set by the controller 28.
In order to minimize phase error in high-speed frequency tracking, maximum gain is desired in the phase-lock loop for the low-frequency synthesizer 16. This can be achieved by using two integrators 56 and 58, rather than one. A phase-lock loop with two integrators, such as integrators 56 and 58, is conventionally known as a type III loop.
The transient response of the type III phase-lock loop shown in FIG. 2 is determined by the location of the poles and zeros in the loop bandwidth. For a type III phase-lock loop (two integrators 56 and 58), typically each integrator has a pole at 0 Hz and a zero somewhere between one-half and one-tenth of the loop bandwidth. These zeros are the dominant elements in determining overall transient response characteristics of the type III phase-lock loop.
For example, a type III phase-lock loop with a loop bandwidth of 100 kHz could have two integrators 56 and 58, each with a pole at 0 Hz and a zero at 10 kHz. This would result in a type III phase-lock loop with minimal ringing and overshoot for large changes in the divide number N and, hence, large changes in the frequency of the VCO 60.
In order to enhance phase-noise performance in a type III phase-lock loop, one conventional technique is to include a passive lag-lead network 64 between the second integrator 58 and a tune voltage input of the VCO 60, as shown in FIG. 2. In the given example, the second integrator 58 would still have its pole frequency at 0 Hz, but would shift the zero down to a low frequency, such as 25 Hz. The lag-lead network 64 would have a pole at this same frequency to cancel the zero and a zero at the original circuit location (in the above example, 10 kHz). The overall response of the second integrator 58 and the lag-lead network 64 would be equivalent (a pole at 0 Hz and a zero at 10 kHz), but any broadband noise at the output of the second integrator would be greatly attenuated by the lag-lead network. The result is improved phase-noise performance.
Transient response and/or stability of the phase-lock loop for the low-frequency synthesizer 16 are major design considerations. The phase-lock loop must settle quickly when the divide number N is changed to sweep the frequency of the low-frequency synthesizer 16 and, hence, the frequency of the microwave oscillator 12 shown in FIG. 1. The greatest demand is placed on the phase-lock loop of the low-frequency synthesizer 16 when the change in N is large.
Now, the stability of the phase-lock loop for the low-frequency synthesizer 16 can be divided into two components: small-signal stability and large-signal stability. Small-signal stability is defined as the transient response to small changes to N, with the resulting transient control voltages within the phase-lock loop of the low-frequency synthesizer 16 less than their saturation limits. Large-signal stability is defined as the response to large changes in N, with the integrators 56 and 58 entering into their saturation region. Under this large-signal operating condition, the operation of the phase-lock loop of the low-frequency synthesizer 16 is no longer linear.
A major limitation of the conventional low-frequency synthesizer 16 shown in FIG. 2 is its large-signal transient response. With a cutoff frequency of 25 Hz, the slew time during large changes in N is considerable. In order to discharge a capacitor 64A of the lag-lead network 64, the second integrator 58 swings to its negative rail, with the first integrator 56 at its positive rail. As the first integrator 56 recovers from saturation, it pulls the second integrator 58 out of saturation also. However, there is a lag time between the change in the output voltage of the first integrator 56 in response to the change in the output of the second integrator 58, as well as the output of the lag-lead network 64. This lag time creates a phase shift in the type III phase-lock loop, which results in instability. This instability appears as ringing in the transient response of the low-frequency synthesizer 16 at best, or as oscillation at worst.
Considered in more detail, FIG. 3 illustrates the transient response of the low-frequency synthesizer 16 shown in FIG. 2 during large-signal operation in response to a large change in the divide number N. When the divide number N is altered from a large number to a small number, the frequency of the VCO 60 switches from a high value to a low value. At the time that N is altered, the output of the first integrator 56 swings positive, the output of the second integrator 58 swings negative, the capacitor 64A of the lag-lead network 64 is discharged, and the frequency of the VCO 60 decreases. As the frequency of the VCO 60 continues to decrease past the desired frequency, the output of the first integrator 56 then goes negative to compensate. However, the time delay between the output of the first integrator 56 and the change in the output of the lag-lead network 64 is too great, introducing excessive phase shift and, hence, instability, as indicated by the arrow shown in FIG. 3.
Sharpe, C. A., "Speed up PLLs," Electronic Design 24, (Nov. 22, 1977) discloses speed-up circuitry to improve phase-lock loop acquisition time. Three approaches are suggested. The first approach is to detect large changes in the divide number N and slew the VCO at a rate faster than normal phase-lock loop dynamics allow by switching between two VCOs operating at different frequencies or range-switching one VCO with capacitors in an associated tank circuit, but the exact frequency shift needed must be known. The second approach is to select circuit values to optimize the slew rate without sacrificing the other phase-lock loop characteristics. The third approach is to tune the VCO frequency coarsely with channel information using a summing network, or with a tuning voltage using varactors, along with frequency lock-in by the phase-lock loop. These approaches are relatively restrictive and complex. In any event, stability of the phase-lock loop is not addressed, and, consequently, stability problems persist.
Therefore, there is a need for a phase-lock loop for a low-frequency synthesizer which has improved acquisition time and stability. It is also desirable to incorporate such a low-frequency synthesizer into a swept synthesized source to yield a swept synthesized source having improved frequency accuracy and reduced phase noise over a broad range of operating frequencies.